Job Description

description of job

STA Synthesis Engineer

We are looking out for an Experienced STA/Synthesis Engineer for our new project with our customer who is a pioneer in the Telecom domain.

Experience Level: 5+ years

  • Experience in ASIC, SoC or FPGA logic design
  • At least 5 years of related experience
  • Expert in VHDL/Verilog/System Verilog
  • Excellent knowledge of:  DC/PC/ICC1/ICC2
  • Synthesis experience for Timing/Area/Power closure
  • multi Core CPU Architecture Knowledge
  • Experience in using TCL/Python/Perl/etc.…
  • Have worked with Environment like Linux, ClearCase, LSF

For more information get in touch with Vaishak Asok at vaishak.asok@swediumglobal.com

Job Overview

  • Location : Remote, Anywhere
  • Vacancy : 1
  • Key Skills : STA, Synthesis, PrimeTime